When your FPGA design fails to synthesize or fails to operate as expected on the board, the cause may not be obvious and the source of the failure may be hard to pinpoint among potentially thousands of RTL and constraint source files, many of which may have been authored by another designer. Last Modified: If you have any questions or concerns about this document. Execute the following command to run Synplify Pro in batch mode: synplifypro batch -licensetype synplifyproactel -batch -log synplifypro.log Tclscript.tcl. A Text Editor for Constraint Files (Legacy) Tcl Syntax Guidelines for Constraint.Running Synplify Pro ME in batch mode requires a floating license (paid or free). Courier Code examples.Editor's Note: This article appeared in the autumn 2012 edition of Xcell Journal magazine, and is reproduced here with the kind permission of Mike Santarini, Publisher and Senior Manager, Xcell Journal and Editorial Services, Worldwide Communications, Xilinx.1 Synopsys FPGA Synthesis Synplify Pro for Microsemi Edition User Guide.
You can save time by performing rudimentary design setup checks on clocks, constraints and module-level interfaces with a view to making your design specification good, before you waste hours in synthesis and place-and-route (P&R).Synopsys’ Synplify Premier and Synplify Pro FPGA design tools and Identify RTL Debugger are among the products available to designers to handle these tasks. Synopsys Synplify/Synplify Pro (L-2016.03)(3)It is essential to apply smarter techniques to isolate specific errors under specific conditions, relate parts of the circuit that are behaving badly back to the source and apply the incremental fixes. Functionality for exporting files from Vivado (IP and IP Integrator) to use in external.
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You can then relate your observations back to the original RTL to narrow down the cause of the problem, which may reside in the RTL specification or constraints setup.Step 1: Specify probes. Let’s examine how to find errors using board-level debug software.By following a four-step approach with an RTL debugger, you can pinpoint and then sample signals and conditions of interest. To debug the design, it is necessary to create additional circuitry and preserve certain nodes so that you can probe, tap and analyze data produced by the design under operation.
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You can switch between signal groups of interest on the fly, without having to spend time re-instrumenting, and resynthesize a newly instrumented design.Unfortunately, the very debug IICE logic that enables you to probe and sample data will consume chip resources, including memory Block RAMs. This strategy increases the signals and conditions that you can observe without increasing data storage requirements. Multiplexed sample groups allow designers to selectively sample and switch between groups of signals through a multiplexed path and shared IICEs. A common problem with on-chip debug methodologies is that it can be difficult to predict ahead of time which signals to probe and monitor.Some debug software solves this problem to a degree by allowing you to take a divide-and-conquer approach. From this RTL schematic you cross-probe back to your original RTL, to adjust it if the design does not appear to be specified as intended, and to the constraints editor, where you can update and more easily specify constraints (Figure 1).Probing all signals is out of the question in a big design, since the amount of data generated would be astronomical and the amount of additional debug logic required to probe the data too great. The viewer includes an RTL View, available after the synthesis RTL compile phase, in which a design is schematically represented by technology-independent components such as adders, registers, large muxes and state machines.
An efficient way to deal with this problem is to have the FPGA synthesis software convert the clocks. When performing FPGA-based prototyping, it is necessary to render ASIC design source files “FPGA ready.” One example is the need to achieve gated clock conversion.Gated clock structures in an ASIC that you may be prototyping in an FPGA are not necessary in the FPGA implementation, and cause inefficient use of FPGA resources. Thousands of RTL and constraint source files can turn that first successful synthesis and place-and-route run into a multiweek endeavor. This approach has the added benefit of increasing the depth of sample data that you can capture.Design errors may be occurring that prevent a clean synthesis and P&R run.
Clock conversion may fail upon the first attempt due to missing clock constraints, where a clock that feeds a sequential element is missing, or due to misplaced clock constraints, in which a clock has become disassociated from its true source for some reason, such as the creation of a black box between the clock source and its destination. On the GCC & Prototyping Tools tab, click on the Clock Conversion checkboxSet_option -fix_gated_and_generated_ clocks 1Performs gated and generated clock conversion in Synplify Pro/Premier, whilePerforms gated-clock conversion on muxes or OR gates in the clock tree in Synplify Premier for Synopsys HAPS-based designs.A “complete” set of clock constraints includes having the clock defined in all the correct places and having defined relationships between the generated clocks. This allows you to tie sequential elements directly to the source clock, removing skew issues and reducing the number of clock sources required in the design, saving resources.To enable the Gated Clocks option in the Synplify Premier software:
Check the Gated Clock Report right after synthesis compilation to find out which clocks failed to convert successfully and why. Figure 2 shows an example of the report.Figure 2. Another list of clocks that did not convert contains an error message explaining why. A Gated Clock Report, available after the compile stage of synthesis, tells you which gated and generated clocks converted and their clock name, type, group and associated constraints. For example, there might be a combinatorial loop in the gating logic that needs to be broken via an exception constraint before clock conversion can occur.
When instantiating IP or preverified hierarchical blocks in a design, “port mismatch” specification mistakes are a common problem and can be difficult to fathom, especially when they occur in mixed-language designs. Each converted instance and clock pin driving the instance is assigned a searchable property and can thus be identified in the design database and extracted into a custom TCL/Find script-generated report.A design can include files that originate from multiple sources both inside and outside of your company. For example, by using the syn_gatedclk_clock_en directive you can specify the name of the enable pin within a black box, while the syn_gatedclk_clock_en_polarity directive indicates polarity of the clock enable port on a black box. ( Click Here to see a larger, more detailed version of this image).If, for example, there are black boxes in your design, you can assist automated gated clock conversion further by specifying software-specific directives in your RTL.
Synplify Premier software, for example, will flag a mismatch immediately and cite it in a separate log report as a hyperlinked error:Interface Mismatch between View work.sub.syn_black_box and View work.sub.verilogThe following bit ports in the Source View work.sub.syn_black_box do NOT exist in the Target View work.sub.
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